This disclosure relates to an inverter circuit suitable for a display unit, and to a display unit provided with the inverter circuit.
An inverter circuit may be formed by an n-channel MOS transistor and a p-channel MOS transistor that are combined on a single chip, or may be formed only by a single channel MOS transistor. The latter is advantageous over the former in terms of productivity and yield, in that the number of process steps is reduced.
FIG. 32 illustrates an inverter circuit 10 structured only by the n-channel MOS transistor according to a comparative example. For reference, a circuit similar to the inverter circuit illustrated in FIG. 32 is described in Japanese Unexamined Patent Application Publication No. 2009-188749. The inverter circuit 10 illustrated in FIG. 32 has a configuration in which two n-channel MOS transistors T10 and T20 are connected in series. The inverter circuit 10 is inserted between a negative voltage line L10 to which a voltage Vss is applied, and a positive voltage line L20 to which a voltage Vdd is applied. The transistor T10 has a source connected to the negative voltage line L10, a drain connected to a source of the transistor T20, and a gate connected to an input terminal IN. The transistor T20 has a diode connection in which a gate and a drain are connected to each other. More specifically, the transistor T20 has the source connected to the drain of the transistor T10, and the gate and the drain which are connected to the positive voltage line L20. Further, a connection point C between the transistor T10 and the transistor T20 is connected to an output terminal OUT.